On the basis of analyzing the common methods of background magnetic field compensation, a new automatic compensation method based on sample and hold circuit is put forward. 在分析磁通门常用背景磁场补偿方法基础上,提出一种新的采样保持电路自动补偿方法。
This AGC system adopts a VGA structure with CMFB and a peak-detect circuit having sample and hold function, and constructs a new-style exponential control circuit. AGC环路中,采用了带共模反馈的VGA结构,包含一个改进的具有采样保持功能的峰值检测电路,并构造了一种新型的指数控制电路。
Design of Sample/ Hold Circuit for High-Speed 14-Bit A/ D Converter 一种用于高速14位A/D转换器的采样/保持电路
A High Resolution Low Power Sample and Hold Module Dedicated to a Pipelined ADC 一个用于流水线模数转换器的高精度、低功耗采样保持电路
The part features very tight aperture delay matching between the two input sample and hold amplifiers. 该器件的两个输入采样保持放大器之间具备高匹配度的孔径延迟。
A High Performance CMOS Sample and Hold Circuit 一种高性能CMOS采样/保持电路
Series and products of nonlinear circuits for semiconductor integrated circuits-Products of sample/ hold amplifiers GB/T12844-1991半导体集成电路非线性电路系列和品种采样/保持放大器的品种
A Method of Background Magnetic Field Compensation for Fluxgate Sensors Based on Sample and Hold Circuit 采样保持电路法补偿磁通门传感器背景磁场
High Performance Sample and Hold Circuit for Pipelined ADC 适用于流水线ADC的高性能采样/保持电路
Simulation and Analysis of Capacitor Mismatch Error in Sample and Hold Circuit 对采样保持电路中电容失配的误差分析与仿真
Its advanced current sensing circuitry employs sample and hold methods to provide a precise average current signal. 其先进的电流检测电路采用采样和保持方法,以提供精确的平均电流信号。
Analysis and measurement of characteristics of correlated clamp sample and hold circuit 相关箝位采样保持(CCSH)电路特性的测量与分析
METHODS: An impedance measurement system was designed and implemented by timer, analog switch, sample and hold amplifier and A/ D board. 方法:通过定时器、模拟开关、采样保持放大器、A/D板等设计并实现脉冲激励阻抗测量系统。
The receiver circuits in the chip adopts novel optimized topology in order to increase the precision of sample, hold and process; 在接收器电路的设计中,论文采用了经优化的新型拓扑结构,提高了数据采样和接收精度;
For the design of high resolution A/ D converters, the design of the sample and hold circuit is very important. Here the bottom plate technique is employed, which can cancel the charge injection error. 在高分辨率的A/D转换设计中,采样/保持电路的设计也是非常重要的,本设计采用了下极板采样技术,可以有效地避免电荷注入效应引起的信号失真。
The Study on Sample Hold 样品支撑初探
Design of a deep sub-micron full differential sample/ hold circuit 深亚微米全差分采样/保持电路设计
The system features the advanced sample hold technique and repeating external trigger model in hardware design as well as the module structure in software design. 该系统的硬件采用较先进的采保和重复外触发技术,软件采用模块化结构。
A low distortion, high speed switched capacitor sample and hold circuit has been designed. A novel bootstrapped switch is used to degrade the nonlinearity and the method to decrease the settling time of the amplifier is proposed. 设计了一种低失真、高速的开关电容采样保持电路,采用了新型的bootstrapped开关来降低由于开关引入的非线性,并提出了减小放大器的建立时间以减小运算放大器引入的非线性的方法。
MDAC has functions of digital-to-analog conversion, subtraction, residue amplification and sample/ hold through charge redistribution between input capacitors and feedback capacitors, which simplifies the structure of the ADC. 通过电荷在输入电容和反馈电容之间的重新分配,MDAC可精确地实现减法和余数的放大,同时极大地简化了电路结构。
The Design of Low Distortion High Speed Sample/ Hold Circuit 低失真与高速采样保持电路的设计
The sample and hold circuit is employed by the bottom plate sampling technique, which could not only cancel the charge injection error but also eliminate the effect of clock feed-through. 采样保持电路设计采用了电容下极板采样技术,不仅有效地避免了电荷注入效应引起的采样信号失真,而且消除了时钟馈通效应的不良影响。
The key pan MDAC has functions of digital-analog conversion, subtraction, residue amplifying and sample/ hold, which simplify the circuit structure and improve the performance of the ADC. 其核心模块MDAC集数模转换、减法、余差放大和采样保持功能于一身,简化电路结构,提高模数转换器的性能。
Sample and hold circuit ( S/ H) is a critical module in pipelined ADC, which is located at the beginning of the signal processing chain. Its speed and resolution restrict the maximum conversion rate and maximum resolution of the ADC. 采样保持电路是流水线型ADC中的关键模块。它位于转换器信号处理链的最前端,它的速度和分辨率决定了整个转换器所能达到的最大转换速度和最高分辨率。
The key circuit design includes a sample-and-hold gain circuit using switched-capacitor to sample or hold the signal and a preamplifier-latch comparator using two-phase clock. 在电路设计中主要包括开关电容采样的全差分运放组成的采保增益电路和两相时钟控制的带预放大器的锁存比较器。
Important blocks such as the Sample and Hold circuit are analyzed in detail. 详细讨论了采样保持电路等核心单元的设计。
A detailed description on the development of explosion flame temperature system of hardware and software was given. The hardware circuit mainly includes I/ V conversion circuit, three-stage amplifier, sample and hold circuit, A/ D convert circuit and external expanding memory. 论文详细阐述了该爆炸火焰测温系统的硬件和软件设计,硬件电路主要包括I/V转换电路,三级放大电路,采样保持电路,以及A/D转换电路和外扩存储电路。
Although this mode can freely adjust integration time, enhance the signal to meet the high-resolution, high sensitivity, high-speed infrared detection needs; but in chip design, the integration amplifier and sample and hold circuit will be contained in a limited area of each pixel. 虽然这种模式可以自由调节积分时间,使信号增强,满足高分辨率、高灵敏度、高速红外探测需求;但是在芯片设计中,要求有限的像元面积内包含积分放大电路和采样保持电路。
A front-end sample and hold circuit is maintained to ensure the performance when the frequency of the input signal is higher than the nyquist frequency. 为了保证采样高于奈奎斯特频率的输入信号时的线性度,输入端依然采用了采样/保持电路。
Sample and Hold circuit built-in DAC saves circuit costs and chip area. 采样保持电路内置于DAC,节省了电路开销和芯片面积。